1. Field of Invention
The present invention relates to a method of manufacturing integrated circuit. More particularly, the present invention relates to a method of manufacturing the gate of a metal-oxide-semiconductor (MOS) device.
2. Description of Related Art
Because refractory metal silicide has the special properties of a high melting point, thermal stability and low resistivity, it is now extensively used in the fabrication of VLSI devices in semiconductor industry. Refractory metal silicide is usually formed between a silicon layer and an aluminum layer for improving their ohmic contact. The refractory metal silicide is also formed as part of the metallic layer in a MOS gate. The most commonly used refractory metal silicide comprises tungsten silicide (WSi.sub.x).
Polycide layers are now routinely used in commercial VLSI production processes that involve the formation of gate conductive layers. Tungsten silicide is normally deposited over other material using a low-pressure chemical vapor deposition (LPCVD) or a sputtering method. After the polysilicon layer and the tungsten silicide layer are properly deposited, photolithographic and etching operations are used to pattern the polycide layer to form the gate structure of a MOS. Since the line width of a conductive layer must be controlled precisely, the polycide layer must also be etched using an anisotropic dry etching operation.
FIGS. 1A through 1D are cross-sectional views showing the progression of manufacturing steps in forming the gate structure of a MOS device according to a conventional method.
First, as shown in FIG. 1A, a semiconductor substrate 100 is provided. Then, a polysilicon layer 102, a tungsten silicide layer 104 and a silicon nitride layer 106 are sequentially formed over the substrate 100. For example, the polysilicon layer 102 can be formed using a low-pressure chemical vapor deposition (LPCVD) method, the tungsten silicide layer 104 can be formed using a physical vapor deposition (PVD) or LPCVD method, and the silicon nitride layer 106 can be formed by again using a LPCVD method. Since a high temperature is required when silicon nitride is deposited over the tungsten silicide layer 104, re-crystallization of the tungsten silicide layer 104 occurs. Consequently, crystal grains are formed in the tungsten silicide layer 104, resulting in the formation of a great many grain boundaries.
Next, photolithographic and etching operations are carried out to remove a portion of the polysilicon layer 102, the tungsten silicide layer 104 and the silicon nitride layer 106 as shown in FIG. 1B. The remaining polysilicon layer 102a, tungsten silicide layer 104a and silicon nitride layer 106a form a composite gate structure 107.
Next, a rapid thermal oxidation (RTO) at 1050.degree. C. of the sidewalls of the gate structure 107 is carried out as shown in FIG. 1C. The reason for performing the RTO operation is to form an oxide layer 108 over the sidewall of the gate structure 107 so that the gate structure 107 is protected. In addition, plasma induced damage during gate etching stage also can be annealed out by RTO. However, since the tungsten silicide layer 104a has great many grain boundaries, the rapid temperature rise and rapid oxidation in a RTO operation leads to the irregular growth of grains inside the tungsten silicide layer 104a. Ultimately, a tungsten silicide layer 104b as shown in FIG. 1C is formed. Irregular grain growth inside the tungsten silicide layer 104a is due to high reactivity at the grain boundaries. Therefore, reactive gases for carrying out the oxidation can easily penetrate into the interior of the tungsten silicide layer. Consequently, tungsten silicide material in the interior is also oxidized, thereby forcing its way out through the sidewalls of the gate structure. Hence, originally flat sidewalls of the gate structure now have protrusions in places where the tungsten silicide layer 104b is located.
Next, as shown in FIG. 1D, silicon nitride spacers 110 are formed covering the oxide layer 108 on the sidewalls of the gate structure 107. Since the tungsten silicide layer 104b has created some protrusions along the sidewalls of the gate structure 107, spacers 110 are unable to fully cover the tungsten silicide layer 104b. This may lead to a short-circuiting of the ultimately formed integrated circuit device. Consequently, product yield is be low.
In light of the foregoing, there is a need to improve the method of forming the gate structure of a MOS device.